Principal SoC Signoff Engineer

Overview

Principal Engineer, SoC Signoff who defines and drives timing constraints across functional and test modes for full chip, complex IP and SoC designs, and leads and mentors engineers.

What you'll do

• Own and drive all phases of constraint development for complex SoCs and complex Digital, AMS and SERDES IPs.
• Define margins for ASIC implementation and STA sign-off, from spec to production.
• Establish process to support MV/DVFS STA signoff and shift-left methodologies for STA.
• Technically mentor a high-performing team and new college graduates.
• Champion the development, deployment and maintenance of STA methodologies using AI/ML with leading EDA tools.
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety and Security requirements and programs.

What you'll need

• Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of industry experience.
• At least 2+ years in subsystem RTL design.
• 6+ years in writing STA constraints.
• 4+ years in STA signoff.
• Deep hands-on expertise in constraint development, functional and test modes, for full chip, sub-chip digital, analog, mixed signal and source-synchronous designs/interfaces.
• Expert in writing constraints for MV/DVFS, advanced in UPF and expert in SDC.
• Expert in STA sign-off margining and has set up process to establish grounds-up.
• Deep hands-on expertise in STA signoff execution, including mode reduction and methodology infrastructure.
• Has carried out timing signoff reviews for SoCs in production.
• Strong proficiency with Synopsys, Cadence, or Siemens/Mentor EDA tools.
• Excellent leadership and communication skills.
• Strong analytical mindset.

Nice to have

• Proven track record of delivering custom silicon across diverse application domains.
• Inspirational leadership style with a passion for mentoring and scaling high-performance teams.
• Customer-centric, proactive problem solver.
• Passion for continuous learning and driving adoption of industry best practices.
• Synopsys EDA tool set expertise.
• Agentic AI exposure.

Details

• Location: Bengaluru, Karnataka, India.