Senior STA Engineer

Overview

Senior STA Engineer responsible for static timing analysis and physical implementation aspects of ASIC and IP development.

What you'll do

• Perform static timing analysis for ASIC designs.
• Develop and apply timing constraints.
• Fix critical timing bottleneck paths.
• Prepare complex ECOs for timing convergence across multiple corners.
• Optimize power and push PPA improvements.
• Support high-performance and low-power implementation methods.

What you'll need

• 3+ years of experience in static timing analysis, constraints, and physical implementation.
• Experience with PT, Tempus, GENUS, Innovus, and ICC tools.
• Expertise in Perl and TCL.
• Strong fundamentals in ASIC engineering.
• Bachelor's degree in Science, Engineering, or a related field with 2+ years of related experience.
• Master's degree in Science, Engineering, or a related field with 1+ year of related experience, or a PhD in a related field.

Nice to have

• Experience with deep submicron process technology nodes.
• Knowledge of high-performance and low-power implementation methods.

Details

• Location: Noida, Uttar Pradesh, India.