Overview
Wireless HW Design Engineer (ASIC) Lead/Senior BDC focused on WRD (Wi‑Fi) design for Qualcomm’s Wi‑Fi chips. You will design Wi‑Fi PHY IPs and support the full RTL lifecycle from spec understanding to RTL coding, QA, and release.
What you'll do
- Design one of the IPs for the Wi‑Fi PHY for an upcoming Wi‑Fi standard.
- Contribute across the design lifecycle: spec understanding, micro-architecture, RTL coding, RTL QA, and releases.
- Participate in requirements-phase discussions with the Wi‑Fi PHY systems team.
- Implement signal processing modules of Wi‑Fi in RTL and/or HLS.
- Build RTL micro-architecture, coding, and validation for linting and CDC rules.
- Work with the functional verification team on test-plan development and debugging.
- Develop timing constraints for RTL synthesis, if required.
What you'll need
- MTech/BTech in Electronics & Communication Engineering with 5–7 years in design, micro-architecture, and RTL coding.
- Verilog and System-Verilog programming proficiency.
- Solid RTL QA flow experience including PLDRC and CDC (CLP optional).
- Strong debugging and problem-solving skills.
- Background in signal processing concepts/algorithms and Wi‑Fi standards is required to implement signal processing modules.
- Scripting language experience (Perl, Tcl, etc.) is required.
Nice to have
- Experience with HLS.
- Working experience in Implementation or STA flows.
- Knowledge of signal processing concepts/algorithms and Wi‑Fi standards (802.11a/b/g/n/ac/ax).
Details
- Location: Bangalore, India.
Read the full description and apply on the company’s own careers page.
