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Digital-electronics Questions Set 104:

Quiz Mode

Which of the following logic gates has an inhibiting input?

AND Gate

NOT Gate

XOR Gate

INHIBIT Gate

Solution:

Which of the following is an example of idempotency?

X.(X+Y) = X

(X+Y).(X+Y') = X

X.X.X. … .X = X

X+X.Y = X

Solution:

Which type of multi-vibrator has a quasi-stable state?

Monostable

Bistable

Astable

Both monostable and bistable

Both monostable and astable

Solution:

The fastest type of analog-to-digital converter (ADC) available is:

Flash ADC

Successive approximation ADC

Dual slope converter ADC

Sigma-delta ADC

Solution:

Which method reduces the number of cycles of operation in a multiplier?

Wallace trees

Dadda multipliers

Baugh-Wooley algorithm

Modified Booth encoding

Solution:

For a digital-to-analog converter (DAC), the required resolution is 50 mV and the total maximum input is 10 V. The number of bits required is:

200

Solution:

Which combination of logic gates can decode the binary number 1111?

One 4-input AND gate

One 4-input AND gate, one OR gate

One 4-input NAND gate, one inverter

Solution:

A 0-5 up counter consists of 3 flip-flops and a combinational circuit block. Which of the following gates is part of the combinational circuit block?

one NOR gate

two AND gates

two NOR gates

one AND gate

Solution:

In a CMOS inverter, if the load capacitance C_L = 3 pF, the pull-up network resistance R_PUN is 100 ohms, and the pull-down network resistance R_PDN is 50 ohms, what is the fall time of the CMOS inverter?

660 ps

330 ps

220 ps

110 ps

Solution:

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

Binary

Ring Shift

Clock

Johnson

Digital-electronics Questions Set 104:

Which of the following logic gates has an inhibiting input?

Solution:

Which of the following is an example of idempotency?

Solution:

Which type of multi-vibrator has a quasi-stable state?

Solution:

The fastest type of analog-to-digital converter (ADC) available is:

Solution:

Which method reduces the number of cycles of operation in a multiplier?

Solution:

For a digital-to-analog converter (DAC), the required resolution is 50 mV and the total maximum input is 10 V. The number of bits required is:

Solution:

Which combination of logic gates can decode the binary number 1111?

Solution:

A 0-5 up counter consists of 3 flip-flops and a combinational circuit block. Which of the following gates is part of the combinational circuit block?

Solution:

In a CMOS inverter, if the load capacitance C_L = 3 pF, the pull-up network resistance R_PUN is 100 ohms, and the pull-down network resistance R_PDN is 50 ohms, what is the fall time of the CMOS inverter?

Solution:

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

Solution:

Related Question Sets:

Related Topics:

Digital-electronics Questions Set 104:

Which of the following logic gates has an inhibiting input?

Solution:

Which of the following is an example of idempotency?

Solution:

Which type of multi-vibrator has a quasi-stable state?

Solution:

The fastest type of analog-to-digital converter (ADC) available is:

Solution:

Which method reduces the number of cycles of operation in a multiplier?

Solution:

For a digital-to-analog converter (DAC), the required resolution is 50 mV and the total maximum input is 10 V. The number of bits required is:

Solution:

Which combination of logic gates can decode the binary number 1111?

Solution:

A 0-5 up counter consists of 3 flip-flops and a combinational circuit block. Which of the following gates is part of the combinational circuit block?

Solution:

In a CMOS inverter, if the load capacitance CL = 3 pF, the pull-up network resistance RPUN is 100 ohms, and the pull-down network resistance RPDN is 50 ohms, what is the fall time of the CMOS inverter?

Solution:

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

Solution:

Related Question Sets:

Related Topics:

In a CMOS inverter, if the load capacitance C_L = 3 pF, the pull-up network resistance R_PUN is 100 ohms, and the pull-down network resistance R_PDN is 50 ohms, what is the fall time of the CMOS inverter?